As field effect transistor (FET) devices are scaled down to have channel lengths in the submicron and deep submicron ranges, gate electrical characteristics become increasingly important for both high speed CMOS digital applications as well as high frequency RF applications. CMOS design consideration for high speed digital applications are usually determined by the pull up time and pull down time of each individual gate. Individual gates are associated with a delay time period for signal propagation in PMOS and NMOS gate electrodes. The delay time period, in turn, is inversely proportional to the drive current (Idrive). It is therefore clear that maximizing the drive current will increase the performance speed or Figure of Merit (FOM) of a CMOS device.
This is particularly true for ultra high speed devices such as RF devices, whereby the increase in sheet resistance of the gate electrode structure with decreasing gate structure size, can degrade device high speed performance.
The prior art has proposed various solutions to the problem of gate electrode resistance including widening the upper portion of the gate electrode to reduce an overall sheet resistance since resistance is inversely proportional to a cross sectional area of the gate electrode. For example T-shaped gate electrodes have been proposed whereby a damascene like process is used to backfill an opening defined in a dielectric layer followed by etching the upper portion of the gate electrode to a wider dimension. While this approach has proven effective for gate lengths of larger than about 0.13 microns, as gate lengths decrease to less than about 0.13 microns several problems arise with the prior art process of forming T-shaped gate electrodes.
For example, prior art processes involve at least two photolithographic patterning steps to form the T-shaped gate structure, such photolithographic processes having increasingly stringent process windows including increasingly precise alignment of photomasks with respect to one another. Misalignment of photomasks in the photolithographic patterning processes frequently causes misalignment of the top portion of the gate electrode with the bottom thinner portion that defines a gate length resulting in asymmetric upper portions of the gate electrode. Such asymmetry in turn causes improper alignment of source and drain regions thereby degrading device performance and reliability.
There is therefore a need in the deep sub-micron FET manufacturing art for an improved deep sub-micron FET gate structure and method of forming the same including T-shaped gate structures in order to improve device performance and reliability as well as device scalability.
It is therefore an object of the invention to provide an improved T-shaped gate structure and method of forming the same in order to improve device performance, reliability, and scalability in addition to overcoming other shortcomings in the prior art.